FIG. 1 (PRIOR ART) is a cross-sectional view of a vertical power doubly-diffused metal oxide silicon field effect transistor (DMOSFET). Peripheral body region 3 and central body region 10 together form a single body region 12. Voltages present on the gate electrode 1 can induce a conductive channel 2 to be formed in the P peripheral body region 3 beneath oxide layer 4. If such a conductive channel is formed, current can flow from conductive source electrode 5 on the top of the structure, down into N+ region 6, laterally through the conductive channel 2 formed in P peripheral body region 3, down through the N- epitaxial layer 7, down through N+ substrate layer 8, and to conductive drain electrode 9.
A PN junction (a diode) is, however, also present in this structure between body region 12 and the underlying N- epitaxial layer 7. If source electrode 5 is adequately positive with respect to drain electrode 9, the PN junction between body region 12 and N- epitaxial layer 7 may be forward biased. In such a forward biased condition, holes are continuously injected by body region 12 into N- epitaxial layer region 7. These holes travel toward the drain electrode 9. Conversely, electrons present in the epitaxial layer 7 travel in the opposite direction toward the source electrode 5. To improve the clarity of the drawing, only two electrons and two holes are shown in the forward biased structure of FIG. 1.
If, on the other hand, source electrode 5 has a negative potential with respect to drain electrode 9, the PN junction between body region 12 and N- epitaxial layer 7 may be reverse biased. In such reverse bias conditions, the depletion region of the PN junction extends outward into epitaxial layer 7 from body region 12. The outer contour of this depletion region under high reverse bias conditions is indicated in FIG. 1 by reference numeral 11. Before this depletion region expands, however, the electrons and holes present in the epitaxial layer 7 which were responsible for the forward bias current must first be removed. These electrons and holes are removed from both the part of the epitaxial layer which will become the depletion region and also from the part of the epitaxial layer which will not be depleted. These electrons present in epitaxial layer 7 are removed from drain electrode 9 whereas these holes present in epitaxial layer 7 are removed from source electrode 5.
FIG. 2 (PRIOR ART) shows one possible application of the power DMOSFET of FIG. 1. Four DMOSFETs, T1-T4, are arranged in a H-bridge structure between a high voltage source +HV and ground. Diodes D1-D4 represent the PN junctions present in transistors T1-T4, respectively. This H-bridge circuit drives current through an inductance 25 which may, for example, be the drive coil of an electric motor. To drive current from node N1 through inductance 25 and to node N2, for example, transistors T1 and T4 are turned on while transistors T2 and T3 are turned off. Current therefore flows from high positive voltage +HV, to node N1, through inductance 25, to node N2, and through transistor T4, and to ground. Diode D2 of transistor T2 is reverse biased.
If the motor being driven is then to be turned off, transistors T1 and T4 are turned off. Due to the inductive load of inductance 25, however, the voltage on node N1 may rapidly go negative to a voltage below ground. Diode D2 will therefore become forward biased and will conduct current from ground, to node N1, and through inductance 25. Once the magnetic field of inductance 25 dies, the voltage of node N1 returns to a positive voltage, thereby reverse biasing diode D2 once more.
FIGS. 3A and 3B depict the current and voltage relationships across a diode under such conditions of rapid switching from a forward biased condition to a reverse biased condition. When the diode is forward biased, forward current I.sub.F flows in the diode. During this forward bias time, holes are continuously injected by body region 12 into N- epitaxial layer region 7 such as shown in FIG. 1. Similarly, electrons continuously flow in the opposite direction into body region 12 and toward the source. Therefore, at time 30 when the voltage across the PN junction structure of FIG. 1 is reversed, some electrons and holes are located in layer 7 between the source 5 and drain 9. Under the reverse bias potential, these charges reverse their direction of travel, the holes rushing back to body region 12 and the electrons rushing back toward the drain 9. This rapid reversal of current flow due to the removal of charge from the epitaxial layer 7 is represented in FIG. 3A by the negative current spike 31. This phenomena involving this negative current is known as "diode recovery" and the negative current spike is known as "diode recovery current". Once these holes and electrons which were present in layer 7 due to the forward current have been removed from the epitaxial layer 7, the diode recovery current stops and the depletion region present at the PN junction expands. The expanding depletion region gives rise to a depletion current which flows in a direction opposite to the diode recovery current. When the depletion region stops expanding, the corresponding depletion current stops, and current flow in the diode dies down to substantially zero current as depicted by reference numeral 32 in FIG. 3A.
FIG. 4 (PRIOR ART) shows two layers of a power device, a metal gate electrode 40 and a metal source electrode 41. Metal gate electrode 40 comprises a gate pad 42 and three gate electrode fingers 43A-43C. Each of the gate fingers extends over a portion of the active region of the device. Metal source electrode 41 comprises a source pad 44, a portion 45 which extends over the active region of the device, and a band of termination metal 46 which surrounds the active region of the device.
FIG. 5 (PRIOR ART) shows a plurality of diffused active cells 50 of the active region of the power device of FIG. 4, a gate shield region 51, and a connected field ring 52 which surrounds the active region.
FIG. 6 (PRIOR ART) is a simplified cross-sectional view of the structure of FIG. 5 taken along cross-sectional line A--A. Source electrode 5 represents a portion of portion 45 of source electrode 41 in FIG. 4. In FIG. 6, a sidewall 51A of the gate shield region 51 is laterally disposed from two active cells 50A and 50B of the active region. Under forward bias conditions, both the P+ gate shield region 51 and the body regions of the two active cells 50A and 50B continuously inject holes into the epitaxial layer 7. Electrons flow the opposite direction toward the source electrode 5. These moving holes and electrons constitute a forward bias current.
When the voltage between the source electrode 5 and drain electrode 9 is rapidly reversed, however, some of these electrons and holes are still passing through epitaxial layer 7. These electrons and holes reverse direction and are expelled from the epitaxial layer 7 as diode recovery current. As shown in FIG. 6, some of the holes in the epitaxial layer flow upward into the P+ gate shield region 51 whereas others of the holes flow upward into the body regions of active cells 50A and 50B. Although electron flow also comprises part of the diode recovery current as explained above, these electrons have been omitted from FIG. 6 to improve the clarity of the illustration.
In the prior art device of FIG. 6, however, there is a localized large current flow flowing into the left side of the peripheral body region 3 of active cell 50A. A disproportionately large number of holes from underneath the P+ gate shield region 51 flow laterally to the right and into the left side of active cell 50A which is closest to the P+ gate shield 51. This large localized current arises due to the fact that a larger impedance R exists between P+ gate shield region 51 and the source electrode 5 than exists between the peripheral body region 3 and the source electrode 5. While the metal of the source electrode 5 makes direct contact with the central body region of each active cell such as active cell 50A, the gate shield 51 is connected to source electrode 5 at a location significantly spaced from the gate pad region of the device. FIGS. 4 and 5 show contacts 47 and 48 connecting the gate shield region 51 to source electrode 41. The relatively large impedance R between the P+ gate shield 51 and the source electrode 5 is due in part to the relatively long and thin portions of the field ring 52 which connect the P+ gate shield region 51 to contacts 47 and 48.
Due to this relatively large impedance R, the same initial flow of charge into the P+ gate region 51 and into body region 12 of active cell 50A during diode recovery will result in the voltage of the P+ gate region 51 being less reverse biased than is the body region 12 of active cell 50A. As a consequence, fewer of the holes under the P+ gate shield region 51 will be absorbed into the P+ gate shield region than are absorbed into the more highly reverse biased side of body region 12 of active cell 50A adjacent to the gate shield region 51. The disparity between the voltage levels on the gate shield 51 and the body region 12 of active cell 50A therefore is magnified further.
This larger diode recovery current flowing into the left side of active cell 50A is larger than the diode recovery current which flows into the other active cells (such as active cell 50B) which are located farther toward the center of the active region. As seen in FIG. 6, the right side of active cell 50A and the left and right sides of active cell 50B in the interior of the active region absorb holes from the epitaxial layer 7 in a substantially uniform fashion. Accordingly, there is not a localized concentration of hole flow like there is into the left side of active cell 50A adjacent the P+ gate shield region 51.
The vertical DMOSFET structure of FIG. 6, however, also contains a parasitic bipolar transistor structure. N+ source region 6 of active cell 50A comprises an emitter, peripheral body region 3 or central body region 10 comprises a base, and N- epitaxial layer 7 and N+ substrate 8 comprise a collector. If an adequately large spike of diode recovery current surges through peripheral body region 3 or central body region 10 to the N+ region 6, the base of the parasitic bipolar transistor may become forward biased with respect to the emitter. The parasitic transistor may therefore be turned on.
FIG. 9 represents a typical characteristic of the collector-to-emitter current I.sub.CE versus the collector-to-emitter voltage V.sub.CE of a bipolar transistor. Because there is substantially no base current in the diode recovery situation depicted in FIG. 6, the curve applicable to operation of the parasitic bipolar transistor in FIG. 6 is the curve labelled I.sub.B =0. Because the collector-to-emitter voltage V.sub.CE of the transistor of FIG. 6 is substantially fixed by the circuit in which the DMOSFET device is operating, the parasitic bipolar transistor typically operates along a vertical line such as dashed vertical line 90 in FIG. 9. Accordingly, if the magnitude of the localized diode recovery current flowing from the base to the emitter exceeds current I.sub.1, the parasitic bipolar transistor enters a negative resistance area of operation. As a consequence, the collector-to-emitter current I.sub.CE climbs rapidly due the negative resistance until the collector-to-emitter current reaches the very high current I.sub.2 which is once again in the positive resistance area of operation. This current I.sub.2 is, however, so great that the parasitic transistor is quickly destroyed. Accordingly, it is seen that once a single parasitic transistor of a power device is turned on, that particular parasitic transistor will attempt to conduct substantially all the diode recovery current. As a result, one parasitic transistor located in an active cell adjacent to the gate shield region will turn on and remain on in diode recovery situations so that it destroys itself, thereby causing the entire power device to fail.
Two structures used today in locations such as location A--A of the conventional power devices of FIG. 5 are shown in FIGS. 7 and 8.
The structure of FIG. 7 (PRIOR ART) provides a direct metal connection between the metal source electrode 5 and the P+ gate shield region 51. This connection reduces or eliminates the disparity in impedance between the P+ gate shield region 51 to source electrode 5 connection and the peripheral body region 3 and/or central body region 10 to source electrode 5 connection. The structure of FIG. 7 has a drawback, however, in that the entire undersurface of the large P+ gate shield region 51 is now an effective injector of charge into the underlying epitaxial layer 7 when the PN junction between P+ gate shield region 51 and N- epitaxial layer 7 is forward biased. This structure therefore results in a great number of charges being injected underneath the gate shield region 51 which contributes to the magnitude of the diode recovery current when the polarity of the source-to-epitaxial layer voltage is reversed.
The structure of FIG. 8 (PRIOR ART) is the structure shown in simplified FIG. 6 and described above. This structure does not have a large gate shield region 51 directly connected to the source electrode 5. This structure therefore does not inject as many carriers into the epitaxial layer 6 during forward bias conditions. The structure of FIG. 8, however, has a drawback in that it involves the relatively large impedance R between the gate shield region 51 and the source electrode 5 which results in a concentration of diode recovery current and a turning on of a parasitic bipolar transistor as described above.